Configuration
4.2
JTAG/ICE
Table 4-2. JTAG/ICE Configuration
Designation
S1
S2
S3
R13
R14
Default Setting
Opened
Opened
Opened
Soldered
Soldered
Feature
Disables the ICE NTRST input
Selects ICE Debug Mode or JTAG Boundary Scan Mode
Disables TCK <-> RTCK local loop. If S3 is closed, R13 must be unsoldered.
Enables the ICE RTCK return. S3 must be opened
Enables the ICE RTCK return. S3 must be opened
4.3
Microcontroller Clock
Table 4-3. Microcontroller Clock Configuration
4.4
Designation
R18/R20
S4
J9
Memory
Default Setting
Soldered
Opened
Feature
Enables the use of 18.432MHz crystal. If external clock is used, R18/R20
must be unsoldered and S4 closed.
Slow Clock Setting. See Table 4-1 .
Table 4-4. Memory Configuration
Designation
SDRAM
R31
R32
Default Setting
Soldered
Soldered
Feature
Enables MN7 Chip select access
Enables MN8 Chip select access
NAND Flash (MN6+x)
J34
R34
S6
Closed
Soldered
Opened
Enables the use of NAND Flash (MN6x)
Enables the use of Ready Busy signal
Disables write protect
SERIAL DataFlash (MN9)
J33
S5
Soldered
Opened
Enable the use of the Serial DataFlash?(MN9)
Disables write protect
TWI SERIAL EEPROM (MN10)
4-2
6413C–ATARM–18-Feb-09
R46
R47
Soldered
Soldered
Enables SCL access
Enables SDA access
AT91SAM9G20-EK Evaluation Board User Guide
相关PDF资料
AT91SAM9M10-EKES KIT EVAL FOR AT91SAM9M10
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AT91SAM9RL-EK KIT EVAL FOR AT91SAM9RL
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